1. Field of the Invention
The present invention relates to a constant voltage circuit, which is capable of providing a stable constant voltage, and an analog electronic clock provided with the constant voltage circuit.
2. Background Art
FIG. 2 is a block diagram of an analog electronic clock. The analog electronic clock is comprised of a semiconductor device 81, a crystal 80, a battery 83, and a motor 82. The semiconductor device 81 is comprised of an oscillation circuit 811, to which the crystal 80 is connected, a frequency division circuit 812, a constant voltage circuit 810, which outputs a constant voltage VREG for driving the oscillation circuit 811 and the frequency division circuit 812, and an output circuit 813 which drives the motor 82.
An analog electronic clock is required to minimize the frequency of replacing the battery thereof, so that the semiconductor device 81 is required to reduce current consumption. Methods that have been proposed for reducing the current consumption of the semiconductor device 81 include, for example, a method whereby to reduce the operating current of the constant voltage circuit 810 and a method whereby to intermittently operate the constant voltage circuit 810 (refer to, for example, Patent Document 1).
FIG. 6 is a block diagram of a conventional constant voltage circuit. The conventional constant voltage circuit includes a reference voltage circuit 22 that generates a reference voltage Vref, a differential amplifier circuit 23, an output transistor 10, a feedback circuit 21, a holding circuit 40 composed of a capacitor, and a switch circuit 50.
The conventional constant voltage circuit has the holding circuit 40, which holds the gate voltage of the output transistor 10, and reduces power consumption by intermittently operating the differential amplifier circuit 23 and the like. The operations of the differential amplifier circuit 23 and the feedback circuit 21 are interrupted by a signal Φ1 and the switch circuit 50 is turned off. At this time, the gate voltage of the output transistor 10 is held by the holding circuit 40 at a voltage before the switch circuit 50 was turned off. Unless a load current significantly varies, the constant voltage circuit is capable of outputting the constant voltage VREG.
[Patent Document 1] Japanese Patent Application Laid-Open No. 2000-298523
However, due to the poor transient response characteristics of the differential amplifier circuit 23, the foregoing conventional constant voltage circuit with the reduced current consumption is incapable of maintaining an output voltage in the case where a load current significantly varies. For example, when the motor of the analog electronic clock is driven and the battery voltage rapidly drops, the poor transient response characteristics of the differential amplifier circuit 23 leads to a reduced voltage between the gate and the source of the output transistor 10, inconveniently causing the constant voltage VREG to vary. If the constant voltage VREG drops below an oscillation stop voltage VDOS of the oscillation circuit 811, then the oscillation circuit 811 may lose its stability and stop oscillation.